--
-- VHDL Architecture Sequential_lib.d_ff.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp6241)
--          at - 10:50:19  3-07-2009
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_d_ff IS
   PORT( 
      d   : IN     std_logic;
      ena : IN     std_logic  := '1';
      clk : IN     std_logic;
      rst : IN     std_logic;
      q   : OUT    std_logic
   );

-- Declarations

END s_d_ff ;

--
ARCHITECTURE v OF s_d_ff IS
BEGIN
  
  
    PROCESS(rst, clk)
      BEGIN
        IF rst = '1' THEN
          q <=  '0';
        ELSIF RISING_EDGE(clk) THEN
          
            q <= d;
             
          
        END IF;
      END PROCESS;
      
END ARCHITECTURE v;

